| 1. | In the fec part , rs ( reed - solomon ) code and interleave are chosen as the basic elements of the error correction system at first ; then the coding parameter and data structure are determined based on the results of matlab simulation ; at last , hdl modules are implemented in fpga using verilog hdl , test results and simulation diagrams are presented as well . in the designing process , the proper division of the modules and the cooperation between modules need a lot of consideration , and the top - down method is adopted to solve these questions
在前向纠错的设计部分,文章首先根据系统的误比特率要求选择了rs ( reed - solomon )码和交织器作为前向纠错部分的基本构架,再根据matlab的仿真结果得到了具体的编解码参数和码字结构,最后在fpga中用硬件描述语言veriloghdl实现了各个编解码模块,并给出了测试数据、实现结果及时序仿真波形图。 |
